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» Nowe książki - Ryszard Tadeusiewicz, Jacek Śmietański Pozyskiwanie obrazów medycznych oraz ich przetwarzanie, analiza, automatyczne rozpoznawanie i diagnostyczna interpretacja

Jednym z najbardziej dynamicznie rozwijających się kierunków inżynierii biomedycznej są zagadnienia związane ze wspomaganiem diagnostyki medycznej, a w szczególności z medyczną diagnostyką obrazową. Problemy te są szeroko omawiane i dyskutowane w wydanej niedawno książce autorstwa prof. Ryszarda Tadeusiewicza i dra Jacka Śmietańskiego "Pozyskiwanie obrazów medycznych oraz ich przetwarzanie, analiza, automatyczne rozpoznawanie i diagnostyczna interpretacja" (Wydawnictwo Studenckiego Towarzystwa Naukowego, Kraków 2011, ISBN 978-83-932168-0-2). W polskiej literaturze jest stosunkowo niewiele pozycji dotyczących tej ważnej problematyki, dlatego wydanie tej książki należy przyjąć z należnym uznaniem. Dokonujący się w ostatnich latach postęp technologiczny umożliwił budowę urządzeń obrazowania medycznego, które udostępniły lekarzom nieosiągalne wcześniej możliwości badania wnętrza organizmu człowieka. Urządzenia te wprowadziły nową jakość do diagnostyki medyc[...] więcej»
w zeszycie PRZEGLĄD ELEKTROTECHNICZNY 2011/9a

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» Synchronization test results of oscillator network CMOS VLSI chip

JACEK KOWALSKI

MICHAŁ STRZELECKI

CMOS VLSI chip of synchronized oscillators' network presented in this paper allows for fast segmentation of binary images. There are many approaches to analysis and labelling of such images. This is a very important aspect of biomedical image analysis, for example in analysis mast cell microscopic images in dermatology [10]. An approach implemented in discussed network chip is based on[...] więcej»
w zeszycie ELEKTRONIKA - KONSTRUKCJE, TECHNOLOGIE, ZASTOSOWANIA 2007/4

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» Architecture of image analysis system for implementing parallel digital image processor

PRZEMYSŁAW BRYLSKI

MICHAŁ STRZELECKI

Demand of fast, real time image processing and analysis requires development of new hardware systems suitable to perform this task. In particular, image segmentation is an important part of image processing, with a key infl uence on quantitative results of its further analysis. There are many image segmentation methods including e.g. artifi cial neural networks. One of the recent approaches to this task is a network of synchronised oscillators. Its operation is based on “temporary correlation" theory [1,4], which attempts to explain scene recognition as performed by a human brain. To implement this theory, Wang [1] proposed an oscillator model to emulate brain neural cell and network of connected oscillators for image segmentation. This model is also very suitable for ha[...] więcej»
w zeszycie ELEKTRONIKA - KONSTRUKCJE, TECHNOLOGIE, ZASTOSOWANIA 2010/3

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» Implementation of the parallel digital processor for image analysis using FPGA technology

PRZEMYSŁAW BRYLSKI

MICHAŁ STRZELECKI

The strong demand of fast parallel processing of data results in design and implementation of digital processors in a number of different architectures. One of the possible and promising approaches to parallel data processing is a network of synchronised oscillators [1]. It has been proven that such a network is a reliable tool for image analysis tasks, like segmentation or noise removal. Its operation is based on “temporary correlation" theory [2], which attempts to explain scene recognition as performed by a human brain. Based on elements of this theory, the parallel digital image processor for an image segmentation and analysis was proposed in [3]. The general diagram of the system for image analysis with the use of proposed processor is shown in Fig. 1. The processor is connected with the remaining of the system using TCP/IP protocol to assure its accessibility by many possible units performing image acquisition and other image analysis that can be located in different places. The image processor implements the matrix of active nodes, which correspond to the image pixels. These nodes are connected by weights that depend on gray levels of neighboring pixels. Weight values between nodes are calculated based on pixel intensities. They are stored before segmentation in each particular node. Nodes belonging to the homogeneous image region possess the same unique label. It is assigned during iterative network operation. Proposed digital image processor was implemented in VHDL [8,9] language and simulated in ModelSim software for 8×8 active elements matrix and neighborhood size N = 4. It has been demonstrated that proposed processor could be successfully applied for segmentation of binary images. Discussed processor described in [3] was synthesized for XCS1600E with Xilinx ISE 8.2. The implemented design utilizes approximately 93% slices of chosen FPGA device. In order to reduce a utilization of FPGA logic by a single n[...] więcej»
w zeszycie ELEKTRONIKA - KONSTRUKCJE, TECHNOLOGIE, ZASTOSOWANIA 2011/5

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» FPGA implementation of parallel image processing system

Przemysław Brylski

Michał Strzelecki

During the last decade field programmable gate array (FPGA) devices achieved technology grade competitive to traditional digital processor systems (DPS). Nowadays FPGA offer very high logical capacity, parallel processing possibilities, high speed and flexibility. These features of FPGA devices make them suitable for development of digital image processing systems. The strong demand of fast parallel processing of data results in designing and implementing of digital processor in a number of various architectures. One of the possible and promising approaches to parallel data processing is a network of synchronized oscillators [1]. It has been proven that such a network is a reliable tool for image analysis tasks, including segmentation or noise removal. Its operation is based on the "temporary correlation" theory [2], which attempts to explain scene recognition as performed by human brain. Based on this idea, the parallel digital image processor for image segmentation and analysis was proposed in [3]. Described processor was implemented in VHDL [6, 7] language and simulated in ModelSim software for 8×8 image size. Performed tests confirm that this processor can be successfully applied for segmentation of binary images. In order to reduce a utilization of FPGA logic by a single image processing unit (node), several modifications of the image processor structure were proposed in [4, 5]. As described in [5] a significant reduction of LUTs needed for node realization (more than 15 times) and general purpose registers (more than 6 times) was achieved. These changes also adopted an algorithm of the image processor for more effective operation in the FPGA structure. As a result, implementation of a processor capable to analyse an image of 16×16 pixels in the Xilinx XC3S500E Spartan-3E family device [...] więcej»
w zeszycie ELEKTRONIKA - KONSTRUKCJE, TECHNOLOGIE, ZASTOSOWANIA 2012/5

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» System bezprzewodowej lokalizacji obiektów

PRZEMYSŁAW BARAŃSKI

MARCIN MORAŃSKI

MICHAŁ STRZELECKI

System bezprzewodowej lokalizacji został zaprojektowany w celu automatycznego wyznaczania pozycji obiektów na płaszczyźnie dwuwymiarowej. Składa się on z sieci bezprzewodowych, zasilanych bateryjnie urządzeń nazywanych węzłami. Każdy nowy węzeł (nazywany węzłem lokalizowanym) dołączony do sieci jest w stanie automatycznie wyznaczyć swoją pozycje na podstawie danych odebranych z trzech węzłó[...] więcej»
w zeszycie ELEKTRONIKA - KONSTRUKCJE, TECHNOLOGIE, ZASTOSOWANIA 2008/11

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