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» Rapid prototyping of electrostatically-driven MEMS

STANISŁAW KALICIŃSKI

In general, design and manufacturing of MEMS is a complex, expensive and time consuming process. Usually, it requires a number of iterative steps for verification of initial concepts and for determination of the properties of structural materials [1]. This process has been significantly boosted by several commercial MEMS design and simulation software tools that have been developed in the last decade, such as COVENTORWARE ® or INTELLISENSE® [2, 3]. Still, when using such software, it is very difficult to combine electromechanical properties of MEMS devices with electrical properties of semiconductors. In this case, a classical scheme, namely with a standard manufacturing cycle: design, fabrication, testing may be the only feasible one. For complex designs, this may cause long times to market. In this paper we present a very simple approach that[...] więcej»
w zeszycie ELEKTRONIKA - KONSTRUKCJE, TECHNOLOGIE, ZASTOSOWANIA 2010/6

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» Maskless laser lithography for fast Microand Nanotechnology devices prototyping in ITE

ANDRZEJ SIERAKOWSKI

Production of MEMS/MOEMS on silicon substrates requires specific technological sequences significantly different from those used in fabrication of Integrated Circuits (ASICs). Applications, such as transducers, AFM probes, gripers are 3- dimensional, while ASICs are located within a thin top layer of a substrate. In the case of MEMS/MOEMS the entire volume of the substrate may play an important role being a functional part of the instrument e.g. mirrors, mobile parts of an actuator, bio-cells. To produce such a type of structures, in addition to a standard technological sequence, one may use deep silicon etching processes (wet and plasma). Often used silicon <100> anisotropic etching technology leads to slant-angle sidewalls. Some applications require placing a metal path going across the sloped area. Performing photolithography makes in such a case many difficulties, mainly because of the variable resist thickness. On expanded topographies, where the sloping surfaces exist, the resist layer is thicker close to the lower edges and thinner close to the top surface. In addition, one can observe an effect of decreasing the metal path width situated close the sloping surfaces resulting from additional resist exposure by light reflected from the mirror surface <111>. During developing of a MEMS/MOEMS new application very often is necessary to test more than one option of the design. Especially photolithography processes require such a type of optimization. Vario[...] więcej»
w zeszycie ELEKTRONIKA - KONSTRUKCJE, TECHNOLOGIE, ZASTOSOWANIA 2011/3

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» Design and manufacturing of heterogeneous microsystems for micro- and nanotechnology applications

PAWEŁ JANUS

The potential and growth of microsystem require integration of mechanical, electrical, optical and many more domains within the small dimensions associated with very large scale integration (VLSI). The behavior of the overall system is not just the simple connection of separate mechanical and electrical behaviors, but the simultaneous combination of mechanical, electrical and optical behaviors. The integration of modern MEMS has to be considered on various levels: - materials used for microsystem construction, - processes used for fabrication of the system, - mechanical and electrical properties of the elements of microsystem, - function of overall integrated microsystem including packaging. Therefore modern tool for multi-domain, heterogeneous microsystem modeling and simulation has to allow the designer take into account all these aspects of integration. Modern methodology of MEMS design presented in this paper is based on a system-level, top-down MEMS design process [1]. The objectives of this method are to optimize the function of the devices and to minimize development time and cost by avoiding unnecessary design cycles and foundry runs. This methodology (Fig.1a) uses an initial set of MEMS re quirements to select a design and fabrication approach. Instead of using a layoutdrawing tool to create a 2D model, high-level design techniques use a graphical schematic capture tool to position and connect the model symbols that represent functional blocks (masses, plates, electrodes or micro-fluidic parts) with underlying analytical formula. Because the simulations are run using code-based, six Degree-Of-Freedom (DOF) behavioral models, instead of FEM based or BEM-based partial differential equation models, the simulation time is reduced by orders of magnitude. Once the design is complete a device layout can be generated automatically from the high level description. In next step, 3D PDE Design and manufacturing of h[...] więcej»
w zeszycie ELEKTRONIKA - KONSTRUKCJE, TECHNOLOGIE, ZASTOSOWANIA 2010/4

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» Modelowanie i wytwarzanie mikrosystemów dla zastosowań w chemii i diagnostyce biomedycznej

Krzysztof DOMAŃSKI

W artykule przedstawiono procesy technologiczne mikroinżynierii krzemowej wykorzystane do wytwarzania przyrządów opracowywanych w ramach projektu MNS-DIAG. Kluczowymi procesami dla wytwarzania opracowywanych w ramach tego projektu demonstratorów są: głębokie plazmowe trawienie podłoża krzemowego, procesy łączenia płytek podłożowych z innymi płytkami krzemowymi, ceramicznymi lub szklanymi, procesy elektrochemicznego osadzania metali szlachetnych oraz procesy nakładania i kształtowania warstw polimerowych. Abstract. The development of silicon technology over the last few decades has enabled production of complex integrated circuits and has also contributed to the development of microsystems containing sensors, actuators, and signal processing circuits. Currently, microsystems based on silicon technology, complemented by processes specific to MEMS technology, are widely used in both automotive as well as in chemistry, biology or medicine. The paper presents processes used to manufacture silicon microsystems developed in the fame of the project “Microsystems for biology, chemistry and medical applications". The project goal is to develop a range of biomedical devices and chemical sensors: lab on a chip for determination of psychotropic drugs in saliva samples, diagnostic instruments for analysis of body secretion for fertility and pathological states monitoring, diagnostic instruments for evaluation of bovine embryos, microreactors for cell culture, arrays of chemical sensors for detection of Gramnegative bacteria and MEMS for medical diagnostic equipment. Key manufacturing processes used for fabrication of these devices are: deep plasma etching of silicon substrate, bonding of silicon, ceramic or glass substrates, electrochemical deposition and patterning of noble metals and coating and patterning of polymer layers on silicon and glass substrates. (Preparation Modeling and manufacturing of microsystems for applications in chemistry and bio[...] więcej»
w zeszycie PRZEGLĄD ELEKTROTECHNICZNY 2010/10

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» Mikroprzepływowe immunoczujniki z detekcją amperometryczną

ANNA BARANIECKA

W przypadku nowoczesnych urządzeń analitycznych, takich jak bioczujniki bardzo istotnymi cechami są: niski koszt pojedynczego testu, jak najkrótszy czas w którym można uzyskać wyniki, wielofunkcyjność, duża czułość oraz możliwość analizowania złożonych próbek. Można to uzyskać poprzez zastosowanie układu mikroprzepływowego, amperometrycznego systemu detekcji oraz analitycznych technik immunoenzymatycznych, takich jak ELISA (Enzyme-Linked Immunoassay), czy ELISPOT (Enzyme-Linked Immuno-Spot Assay) [1]. W przypadku detekcji amperometrycznej najczęściej używane są immunoglobuliny z klasy G (IgG) znakowane enzymami, takimi jak: fosfataza alkaliczna, peroksydaza, katalaza, laktaza i galaktozydaza. Istnieje szeroki wybór testów ELISA nadający się do aplikacji w czujnikach do oznacz[...] więcej»
w zeszycie ELEKTRONIKA - KONSTRUKCJE, TECHNOLOGIE, ZASTOSOWANIA 2009/12

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» Implementation of FD SOI CMOS technology in ITE

KRZYSZTOF KUCHARSKI

Fully-depleted silicon-on-insulator (FD SOI) CMOS technology is widely used for fabrication of low-power, low-voltage CMOS integrated circuits (ICs) [1]. Interest in SOI CMOS technology in ITE dates to the late 90s. Different aspects of SOI technology have been considered, e.g. modelling of PD SOI MOSFETs, as well as integration of CMOS on thick SOI substrates with p-n junction based detectors of ionizing radiation [2, 3]. Recent works also comprise development of FinFET-type devices for application as chemical detectors [4]. Thus a variety of SOI CMOS technologies are under continuous development. These applications, except for the FinFET-based one, have not taken advantages of FD SOI technology: better channel operation control by gate voltage, better subthreshold I-V characteristics, lower p-n junction area and capacitance, thus lower leakage, power consumption and higher speed, as well as wider range of temperature operation. In order to fill this gap, a collaboration with UCL has been undertaken, and supported by TRIADE project [5]. The collaboration aims at transferring the FD SOI CMOS technology, originally developed at UCL [1], to ITE. Main features of this process are as follows: supply voltage 3 V, threshold voltage 0.3 V, and min poly-silicon gate width 1.5 μm. In the sections below issues related to the task mentioned above are reported. SOI substrates A recommended method for fabrication of high-quality 4-inch SOI substrates (requirement of ITE facilities) consists in laser cutting of the 200 mm UNIBOND SOI wafers manufactured originally by SOITEC. At present they represent the top quality with respect to thin silicon layer properties (crystallography, Si/SiO2 interface quality, thickness, and its uniformity), which are very relevant for manufacturing of the FD SOI CMOS devices. Method and equipment for laser cutting of 200 mm wafers have been developed in ITE. In Fig.1. the way, in which the 200 mm SOI U[...] więcej»
w zeszycie ELEKTRONIKA - KONSTRUKCJE, TECHNOLOGIE, ZASTOSOWANIA 2011/3

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