» Pros and cons of system-level synthesis of data-dominated algorithms
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PIOTR DZIURZAŃSKI 
In case of multi-core systems, it is practically impossible to simulate
them at low levels of abstraction, owing to its long time
that postpones time-to-market (TTM) for a considered product.
For example, simulating a boot-up sequence of a mobile
phone at a register-transfer level (where entities are registers,
latches, multiplexers, etc.), takes more than six months, whereas
the same simulation carried out on a higher, system level
model level (where each entity resembles program language
objects whose communicate each other executing appropriate
functions), takes about one week (Information obtained during
a private talk with an employee from one of a world top mobile
phone producers).
But the possibilities of efficient synthesis directly from this
level, without rewriting the models into a lower level of abstractions
is still an open questions.
According to the authors knowledge, despite numerous
appeals, nobody published a widely accepted set of benchmarks
for system-level synthesis. Taking into account the
progress in logic design after publishing the ISCAS85 set or
ITC’99 set often used at higher level of digital design, one
may draw the conclusion that this lack of popular benchmarks
hampers the progress in design at this level and
makes the comparison between results of various group of
scientists almost impossible. Similarly, despite a few reports
(e.g. [4] or [8]), in order to compare the hardware synthesis
performed from system and architectural level of abstraction,
one has rather to perform one’s own observations as there
is still, according to the literature study of the authors, no
comparison between these numbers for a wide set of popular
functions. Besides, some brochures or tutorials of EDA
companies (such as [7]) show even that the design from the
system level leads to better results than synthesis from lower
abstraction levels, that is intuitively possible for a rather narrow
classes of probl[...]
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w zeszycie
ELEKTRONIKA - KONSTRUKCJE, TECHNOLOGIE, ZASTOSOWANIA 2010/10
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» Adaptive tree-based multicast routing in network on chip architecture
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ŁUKASZ CZARNECKI PIOTR DZIURZAŃSKI
Modern high-end digital systems require processing between
many heterogeneous functional units. Their demands for efficient
on-chip communication become greater as the number
of systems functional units grows. The performance of such
systems is mainly limited by their communication capabilities
[5]. The new requirements like need for handling mixed types
of traffic, quality of service assurance and even need for sharing
resources caused that the traditional bus-based system
architectures became no longer suitable for such systems.
The integrated circuits evolve, components become smaller,
faster and more powerful, but their complexity grows as well.
While the processing technology is developing at a rather fast
pace, the communication technology remains almost unchanged,
which leads to increasing the unbalance between gate
delays and wire delays on chip [3]. Contemporary high-end
systems most of the power use to drive wires and most of the
clock cycle is spent on wire delay, not gate delay [5].
The main motivation for using on-chip networking is
to achieve better performance. The advantage of NoC is that
only point-to-point one-way wires are used, for all network
sizes, thus local performance is not degraded when scaling,
in contrast to buses where every unit attached adds parasitic
capacitance, therefore electrical performance degrades with
growth [1,3].
Efficient multicast communication when considering scalable
multiprocessor architectures plays very important role.
The message routing algorithm determines the overall system
performance. Since the support for on-chip multicast in current
multiprocessors is very poor (mostly multicast is implemented
as set of multiple unicast messages [10]) the demand for high
effective, low latency algorithms is even greater. Despite the
fact that there are number of multicast algorithms for off-chip
area, they cannot be straightway applied for on-chip domain
because of the tight constra[...]
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w zeszycie
ELEKTRONIKA - KONSTRUKCJE, TECHNOLOGIE, ZASTOSOWANIA 2010/4
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» Path-based multicast routing in network on chip architecture
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MARCIN HAWRANIAK PIOTR DZIURZAŃSKI
Application of many heterogeneous functional units are of
mounting popularity in the current top-end digital systems.
However, the performance of a system’s functional unit is limited
due to the delays of the communication between them [5].
What is even worse, the need for such intense communication
increases as the systems become larger. The architecture of
a conventional bus-based system becomes obsolete due to
the quality assurance, handling mixed traffic and resource
sharing requirements. The computational units become smaller,
much more powerful and faster. Unfortunately, a gap has
been created between processing technology and communication
technology which leads to increasing the unbalance
between gate delays and wire delays [3]. Contemporary highend
systems most of the power use to drive wires and most of
the clock cycle is spent on wire delay, not gate delay [6].
On-chip networking has been introduced in order to tackle
these communication problems. However, a typical Network
on Chip (NoC) uses one-way wires which run from point A to
point B, rather than using buses connected to a number of
destination cores. This makes sending of a single package
to a number of destination nodes (i.e., multicast traffic) more
difficult [1, 3].
Although there are many multicast algorithms for the traditional
TCP/IP networks, they cannot be applied immediately
to the NoC field due to the stringent restrictions imposed by
this architecture. Also multicast support in a modern multiprocessors
is currently very poor, as usually multicast is implemented
as multiple unicast communication [12]. There is still
need of competent multicast communication and the application
of high efficiency, yet low latency, multicast algorithms [5].
Keeping that in mind, we developed an adaptive algorithm for
multicast communication in NoCs.
In general, NoCs use three different groups of components.
These are cores, interconnection channels and router[...]
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w zeszycie
ELEKTRONIKA - KONSTRUKCJE, TECHNOLOGIE, ZASTOSOWANIA 2011/2
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» Flexible packet scheduling algorithm utilization for on-chip networks
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PAWEŁ STOLARSKI TOMASZ MĄKA PIOTR DZIURZAŃSKI
Using contemporary technology, it is possible to implement a
large number of computational units inside a single chip. Such
kind of chip is usually referred to as System on Chip - SoC.
A typical system of this type is usually composed of computational
elements, I/O interfaces, memory, and communication
infrastructure. Due to the continuously increasing complexity of
these systems and low scalability of inner connections, system
cores are connected with Network on Chip (NoC) [1].
These networks are an alternative to the state-of-the-art point
to point or bus-based connections and, similarly to buses, they
offer an universal interface for connecting SoC elements. However,
NoCs guarantee better electrical parameters of transmitted
signals, higher bandwidth and are capobility of tr[...]
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w zeszycie
ELEKTRONIKA - KONSTRUKCJE, TECHNOLOGIE, ZASTOSOWANIA 2009/6
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