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Wyniki 1-1 spośród 1 dla zapytania: authorDesc:"ŁUKASZ CZARNECKI"

» Adaptive tree-based multicast routing in network on chip architecture

ŁUKASZ CZARNECKI

PIOTR DZIURZAŃSKI

Modern high-end digital systems require processing between many heterogeneous functional units. Their demands for efficient on-chip communication become greater as the number of systems functional units grows. The performance of such systems is mainly limited by their communication capabilities [5]. The new requirements like need for handling mixed types of traffic, quality of service assurance and even need for sharing resources caused that the traditional bus-based system architectures became no longer suitable for such systems. The integrated circuits evolve, components become smaller, faster and more powerful, but their complexity grows as well. While the processing technology is developing at a rather fast pace, the communication technology remains almost unchanged, which leads to increasing the unbalance between gate delays and wire delays on chip [3]. Contemporary high-end systems most of the power use to drive wires and most of the clock cycle is spent on wire delay, not gate delay [5]. The main motivation for using on-chip networking is to achieve better performance. The advantage of NoC is that only point-to-point one-way wires are used, for all network sizes, thus local performance is not degraded when scaling, in contrast to buses where every unit attached adds parasitic capacitance, therefore electrical performance degrades with growth [1,3]. Efficient multicast communication when considering scalable multiprocessor architectures plays very important role. The message routing algorithm determines the overall system performance. Since the support for on-chip multicast in current multiprocessors is very poor (mostly multicast is implemented as set of multiple unicast messages [10]) the demand for high effective, low latency algorithms is even greater. Despite the fact that there are number of multicast algorithms for off-chip area, they cannot be straightway applied for on-chip domain because of the tight constra[...] więcej»
w zeszycie ELEKTRONIKA - KONSTRUKCJE, TECHNOLOGIE, ZASTOSOWANIA 2010/4

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