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Wyniki 1-1 spośród 1 dla zapytania: authorDesc:"MARCIN HAWRANIAK"

» Path-based multicast routing in network on chip architecture

MARCIN HAWRANIAK

PIOTR DZIURZAŃSKI

Application of many heterogeneous functional units are of mounting popularity in the current top-end digital systems. However, the performance of a system’s functional unit is limited due to the delays of the communication between them [5]. What is even worse, the need for such intense communication increases as the systems become larger. The architecture of a conventional bus-based system becomes obsolete due to the quality assurance, handling mixed traffic and resource sharing requirements. The computational units become smaller, much more powerful and faster. Unfortunately, a gap has been created between processing technology and communication technology which leads to increasing the unbalance between gate delays and wire delays [3]. Contemporary highend systems most of the power use to drive wires and most of the clock cycle is spent on wire delay, not gate delay [6]. On-chip networking has been introduced in order to tackle these communication problems. However, a typical Network on Chip (NoC) uses one-way wires which run from point A to point B, rather than using buses connected to a number of destination cores. This makes sending of a single package to a number of destination nodes (i.e., multicast traffic) more difficult [1, 3]. Although there are many multicast algorithms for the traditional TCP/IP networks, they cannot be applied immediately to the NoC field due to the stringent restrictions imposed by this architecture. Also multicast support in a modern multiprocessors is currently very poor, as usually multicast is implemented as multiple unicast communication [12]. There is still need of competent multicast communication and the application of high efficiency, yet low latency, multicast algorithms [5]. Keeping that in mind, we developed an adaptive algorithm for multicast communication in NoCs. In general, NoCs use three different groups of components. These are cores, interconnection channels and router[...] więcej»
w zeszycie ELEKTRONIKA - KONSTRUKCJE, TECHNOLOGIE, ZASTOSOWANIA 2011/2

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