Wyniki 1-1 spośród 1 dla zapytania: authorDesc:"Michał STRZYGA"

Simulation based feasibility study of Junction Vertical Slit Field-Effect Transistor (JVeSFET)

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This paper presents simulated DC characteristics of deep-submicron JFETs conforming to the principle of extreme layout regularity, that is a foundation of a new Vertical Slit geometry ICs (VeSTICs) vision proposed in [4]. Exploration of parameter space of this fully symmetrical dual gate JVeSFETs has been performed. As a conclusion an assessment of applicability of these devices in nano-size era SoCs is proposed. Streszczenie. W pracy przedstawiono oparte na symulacjach stałoprądowych studium wykonalności tranzystora polowego złączowego o głęboko submikrometrowych wymiarach, spełniającego wymagania ekstremalnej regularności layoutu wg zaproponowanej przez W. Malego [4] koncepcji pionowej szczelinowej geometrii układow scalonych VeSTIC. Taki symetryczny dwubramkowy JVeSFET proponowany jest do integracji w SoC. (Studium wykonalności złączowego tranzystora polowego o geometrii wertykalno-szczelinowej (JVeSFET)) Keywords: JFET, Vertical-Slit Transistor Integrated Circuit, JVeSFET Słowa kluczowe: JFET, wertykalna szczelinowa geometria układów scalonych, JVeSFET Introduction In last decade applications of junction field-effect transistors have been limited to few constantly shrinking niches, mainly as a pivotal component of radiation hardened analogue/digital circuits [1], [2]. This may change soon. In the deep-submicron era shortcomings of JFETs seem to be less pronounced and advantages to be more attractive. Especially attractive today seem to be: a potential for achieving superior Ion to Ioff ratio, low leakage currents and perhaps high level of radiation immunity as well as low noise [3]. This paper presents a simulation based feasibility study devoted to the deep-submicron JFETs, geometry of which has been dictated by the requirement for an extreme layout regularity that is a foundation of a new Vertical Slit geometry ICs (VeSTICs) vision, proposed by Maly in [4]. Owing to this geometry (Fig. 1) JFETs may be integrated in VeSTICs t[...]

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