Wyniki 1-4 spośród 4 dla zapytania: authorDesc:"Tomasz TALAŚKA"

power-efficient, current-mode, binary-tree min / max circuit for Kohonen self-organizing feature maps and nonlinear filters

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A novel current-mode, binary-tree Min / Max circuit for application in analog neural networks and filters has been presented. In the proposed circuit input currents are first converted to step signals with equal amplitudes and different delays that are proportional to the values of these currents. In the second step these delays are compared using a set of time domain comparators in the binary tree structure that determine Min or Max signal. The circuit realized in the CMOS 0.18 μm process offers a precision of 99.5% at data rate of 2.5 MS/s and energy of 0.5 pJ per input. Streszczenie. W pracy zaproponowano nowy, pracujący w trybie prądowym układ Min / Max oparty na strukturze drzewa binarnego, do zastosowań w analogowych sieciach neuronowych oraz filtrach nieliniowych. W układzie tym sygnały prądowe najpierw zamieniane są na sygnały skoku jednostkowego o równych amplitudach i różnych opóźnieniach. Następnie opóźnienia te porównywane są w komparatorach czasu znajdujących się w strukturze drzewa binarnego wskazującej sygnał o minimalnej lub maksymalnej wartości. Układ zaprojektowany w technologii CMOS 0.18 μm charakteryzuje się precyzją działania na poziomie 99.5 %, przy szybkości przetwarzania danych 2.5 MS/s oraz energii 0.5 pJ na każde wejście. (Nowy, pracujący w trybie prądowym układ Min / Max oparty na strukturze drzewa binarnego, do zastosowań w analogowych sieciach neuronowych oraz filtrach nieliniowych) Keywords: Min / Max operations, analog neural networks, nonlinear filters, CMOS implementation, low energy consumption. Słowa kluczowe: funckje Min / Max, analogowe sieci neuronowe, filtry nieliniowe, implementacja CMOS, niskie zużycie energii Introduction The Max and the Min functions, often called the winner takes all (WTA) and the loser takes all (LTA) operations respectively, are useful in various applications, like artificial neural networks (ANN), signal and image processing and telecommunication systems. In compet[...]

An influence of current-leakage in analog memory on training Kohonen neural network implemented on silicon

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The paper presents how the current leakage encountered in capacitive analog memories affects the learning process of hardware implemented Kohonen neural networks (KNN). MOS transistor leakage currents, which strongly depend on temperature, increase the network quantization error. This effect can be minimized in several ways discussed in the paper. One of them relies on increasing holding time of the memory. The presented results include simulations in Matlab and HSpice environments, as well as measurements of a prototyped KNN realized in a 0.18m CMOS process. Streszczenie. W pracy pokazano jak prąd upływu występujący w analogowych komórkach pamięci wpływa na proces uczenia w sprzętowych realizacjach sieci neuronowych Kohonena (KNN). Prądy upływu w tranzystorze MOS, które mocno zależą od temperatury, zwiększają błąd kwantyzacji sieci. Efekt ten może być minimalizowany na różne sposoby, omówione w pracy. Jeden z nich polega na wydłużeniu czasu przechowywania informacji w komórkach pamięci. Przedstawione wyniki zawierają symulacje w środowiskach Matlab i Hspice, a także badania laboratoryjne prototypu sieci KNN, wykonanego w technologii CMOS 0.18m. (Wpływ prądu upływu w analogowych komórkach pamięci na proces uczenia w sprzętowych realizacjach sieci neuronowej Kohonena). Keywords: analog neural networks, Kohonen networks, memory leakage effect, hardware signal processing Słowa kluczowe: analogowe sieci neuronowe, sieci Kohonena, upływność informacji, sprzętowe przetwarzanie sygnałów Introduction One of the most critical problems in hardware implemented neural networks is how to precisely store information about neuron weights. The way of storing the information depends on type of signals representing the neuron weights as well as on how the network is realized. In this paper, we focus on networks proposed by Kohonen in [1] that are trained in an unsupervised manner. Apart from the Kohonen networks, the obtained results can[...]

A Flexible Winner Takes All Neural Network with the conscience mechanism realized on microcontrollers

  Implementation of ANNs on microcontrollers (μC) is an interesting alternative in comparison with PC-based realizations of such networks [1, 2]. The achievable data rates are in this case usually smaller than in case of NNs realized on PC, but in many applications high data rate is not the most important, while small sizes of a device and relatively low power dissipation are the paramount features. On the other hand, in comparison with the realizations of ANNs as VLSI ASICs that offer ultra low power dissipation and large density and, in consequence, very small device sizes [3, 4], the ANNs realized on μC are much more flexible in terms of reconfigurability. The core blocks in this case are digital that makes such systems much easier in the realization. In this case there is no influence of negative effects present in analog implementation, e.g. the current leakage and the charge injection effects [3]. Winner Takes All ANNs belong to the group of networks trained without the supervision. The training process, in each learning cycle, starts in this case with presenting the network particular learning patterns X from an input data set. For each pattern the network calculates a distance between the X and the weights W vectors in all neurons. Different measures of the similarity between the X and the W vectors are being used. The most popular are the Euclidean (L2) and the Manhattan (L1) measures defined as follows: (1) (2) In the L1 case both the squaring and the rooting operations have been eliminated that significantly simplifies the overall learning algorithm. Both these measures have been used in the proposed implementation of the ANN, for the comparison. Detailed investigations carried out by the authors with various data sets and different numbers of neurons show that the L1 measure offers comparable results, while it requires much less computational resources. The adaptation process of the winning neurons is per[...]

A new, low cost, precise measurement card for testing of ultra-low power analog ASICs

  Measurement of ultra low power high precision ASICs is a challenging task. This is due to low values of the currents and voltages that are often in the noise floor, but also due to very small differences between particular signals that have to be distinguished. An example circuit of this type is the current-mode Gilbert vector multiplier that operates in the underthreshold region with currents not exceeding a few μA [1, 2]. Other circuits of this type include low power summing circuits, dividers, circuits that calculate the exponential and other functions. Circuits of this type are used in low power analog decoders [1], analog filters [2], neural networks [3] etc. In circuits that are to be used as components in low power portable devices, low power operation is one of the paramount features. The proposed measurement card can be used to test circuits working in either the voltage or the current mode. The measurements can be performed in 16 channels in parallel. In the voltage mode the signals in the range from -8 to 8V can be measured with the resolution of 20 μV, while in the current mode in the range from 1 nA to 20 mA with resolution of up to 20 bits. The maximum frequency of a single channel (up to 2 kHz) is sufficient in many applications. For example, in analog FIR filters built on the basis of the Gilbert vector multipliers [2] the most important feature is precision, which has a direct influence on attainable attenuation in the stop-band, while data rate below 1 kHz is acceptable n this case. High precision in the voltage mode has been achieved by the use of the circuits working in the differential mode. In general, the parameters described above have been achieved by the use of various signal converters, filters and amplifiers. In the literature one can find various measurement systems [4-6]. The authors of [4, 5] have proposed a multichannel system to register temperature response of electronic circuits in [...]

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