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Testing of interconnections with use of reduced-size signature-based diagnostic dictionary

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There are distinguished two Interconnect Built In-Self Test (IBIST) categories: test-per-scan [1, 10] and test-per-clock [2-5, 8], which have distinctly different properties. Unfortunately test-per-scan IBIST require long testing time. This drawback does not occur in the test-per-clock IBIST technique, where the testing time is much shorter (i.e. several orders of magnitude) and where there is a potential ability to detect dynamic faults: delay faults, crosstalk and switching noise [6]. A new type of the test-per-clock IBIST structure that has recently become being used for testing of interconnections represents a specific ring register R-LFSR [2, 3], where n lines of the Network Under Test (NUT) act during the test as feedback lines of the LFSR. The cells being in normal operation mode the n transmitters and n receivers of the network lines, during the test constitute a 2n-bit shift register, that together with n lines of the NUT make a R-LFSR. During the test, the R-LFSR generates consecutive 2n-bit pseudorandom test vectors. The half of each vector is a stimulus vector for the NUT. In order to detect a fault in interconnections it is mandatory to find out - for selected initial state SD - such the length m of the sequence of the register states, that the final state (signature) of such a sequence Sm F0 associated with faultfree bus would differ from each state SmFj attributable to a faulty bus. In practice one has to find out the signature Sm F0 for the fault-free R-LFSR unit as well as a set of signatures {Sm Fj } that correspond to defects that were modeled for the bus. In that way the diagnostic dictionary is obtained DD = Sm F0 ∪ {Sm Fj}. 16 Elektronika 11/2010 All methods that employ the ring register and the associated diagnostic dictionary suffer from the problem that consists in fast growth of the dictionary size in pace with the increase of the number of connections under test and multiplicity of the consid[...]

Analysis of operation of ring LFSR used for testing of unidirectional interleaved interconnections

  With regard to the methods how test vectors are applied to the Circuit Under Test (CUT) the Interconnect Built-In Self Test (IBIST) tools are classified into two categories: test-per-scan [7, 12] and test‑per‑clock [6, 9, 10] with characteristic features that are substantially different for the both techniques. The significant advantage of the test-per-clock IBIST structures as compared to the respective test-per-scan structures is the considerably (i.e. by several orders of magnitude) shorter time of test execution and much easier testing of dynamic faults, i.e. delay faults, crosstalks and switching noise [1, 6, 11]. The conventional IBIST structures of the test-per-clock type usually comprise two separate modules: the test pattern generator (usually LFSR) and compactor of output responses (usually MISR) [6, 10, 11]. For the IBIST structure of the LFSR-MISR type the test procedure is independent on the CUT function to be tested. At the end of 80’s the new BIST structure of the Circular Self- Test Path (CSTP) [8] was proposed. The method consists in connection of all the memory modules within the CUT in a single shift register that is then converted into a self-test ring by connection of its output with the input. However, for many years the CSTP structure has never been adopted for testing of pure interconnections. The attempt to apply such a structure to test a bus of unidirectional lines was proposed in [4, 5]. In that case the CTSP becomes an ordinary linear ring LFSR (R-LFSR) [4, 5], where the interconnections under test constitute its feedback lines (Fig. 1). The feedback of the register is described by the characteristic polynomial p(x). It makes possible to apply the techniques dedicated to analysis of the test efficiency that are typical for linear registers and that differ from the method proposed in [8]. It eliminates troubles with analyzing efficiency of test procedures [8] caused by the fact th[...]

Testing of crosstalk-type dynamic faults in interconnection networks with use of ring LFSRs

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The need to apply the test-per-clock method at full clock rates to test crosstalks in networks of long interconnects between modules in a System on a Chip (SoC) is highlighted. Our method involves the 3n-R-LFSR (Ring Linear Feedback Shift Register). The part of the R-LFSR that generates test patterns for n-interconnects has double number of flip-flops where every second flip-flop is connected to the network of Interconnects Under Test (IUT). It has been proved that the 3n-R-LFSR is capable to generate all the two-test patterns that are necessary for IUT. The completed simulation experiments evidenced efficiency of the method application to test crosstalks that are manifested by either a glitch or an edge delay. Streszczenie. Przedstawiono metodę wykrywania przesłuchów w długich połączeniach pomiędzy blokami układów SoC. Wykorzystano liniowy rejestr pierścieniowy R-LFSR. Część rejestru generująca wektory testowe ma podwojoną liczbę przerzutników w stosunku do typowego rejestru pierścieniowego, co drugi przerzutnik połączony jest z testowaną siecią połączeń. Wykazano, że taki rejestr może wygenerować wszystkie pary testów niezbędne do wykrycia przesłuchów. (Wykrywanie przesłuchów w sieciach połączeń z wykorzystaniem liniowych rejestrów pierścieniowych R-LFSR) Keywords: Linear ring register; Test pattern generator; Crosstalks; System on a Chip (SoC); Interconnect network. Słowa kluczowe: Liniowy rejestr pierścieniowy, Generator wektorów testowych, System jednoukładowy, Przesłuchy, Sieć Połączeń Introduction Continuous progress in development of technologies offers the opportunity to place the entire digital system on a singe integrated circuit. Such a System on a Chip (SoC) incorporates embedded modules (cores) that communicate via a network of long interconnections. As integration density of one-chip systems increases, interconnections between the embedded cores are getting more and more crucial for correct and reliable operation of the e[...]

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