Wyniki 1-2 spośród 2 dla zapytania: authorDesc:"Viktor BOLGOV"

Interlock Delay Time and its Influence on the Operability and Efficiency of High-Power DC/DC Converters

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In DC/DC power converters the interlock delay time between IGBT switching on and off in the opposite inverter arms is usually recommended to be 10-20% of the half period to avoid a short circuit in a DC-link. However, in power supplies with extended input voltage variations, much smaller interlock delay time could be used. In this paper the interlock delay time minimization possibility is analyzed on an example of an experimental DC/DC converter with 6.5 kV IGBTs. The possible impact on the converter’s components, operability and efficiency are evaluated. Streszczenie. W celu uniknięcia zwarcia obwodu DC w przekształtnikach DC/DC stosuje się zwykle czas martwy równy 10-20% połowy okresu pracy. W przypadku dużej zmienności napięcia wejściowego wymagane są znacznie krótsze czasy [...]

Mathematical model for assessment of voltage disturbing sources in networks with distributed power generation DOI:10.15199/48.2019.03.12

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Among other challenging topical problems in modern electrical power systems, there are the identification of disturbing sources (DSs) in network and assessment of their contributions into power quality (PQ) deterioration at a point of evaluation (POE). The proliferation of renewable energy sources like PV panels and wind generators in electrical systems is transforming centralized power supply systems (PSSs) into those with distributed generation (DG) and increasing importance of PQ problems. There are still no enough good methods for modelling customers’ installations especially those incorporating generating units. This paper considers how to identify DSs in such installations and assess their impact on PQ at a random POE that is usually some point of common coupling (PCC). The presented study offers DS topologies and the procedure for defining the parameters of a DS equivalent circuit on the basis of standard measurements [1]. There are presently a lot of methods proposed to find a solution for the problem. The contemporary methods used to identify and assess impact of voltage disturbing sources on PQ at a POE are shortly described below. A more comprehensive review can be found in [2-5]. The list of used abbreviations is provided at the end of the paper. Review of existing methods The models based on single-line Thevenin or Norton equivalent circuits (Fig. 1) are the prevailing ones [3-12]. Both a customer’s installation (CI) and an upstream power system (PS) are represented as a voltage source in series with impedance for each sequence q and harmonic. Such an assessment of disturbing sources is simple, but it is applicable only for the case with a single POE, a single CI and a single dominating DS on either utility or consumer’s side. Another disadvantage explained below is a need to have an equivalent circuit for each symmetrical component. There are also some methodological problems related to th[...]

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