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The MPW service development


  The entire work spent for MPW service development can be split into three main parts related to three groups of activities: process characterization, process design kit (PDK) development and logistics issues. The process characterization part, which is the starting point, focuses on measurements of process parameters (e.g. sheet resistance of interconnect layers) as well as parameters of all silicon devices available (e.g. models of all transistor types). Special test structures, dedicated for given sets of parameters are also designed and manufactured at this stage. The second set of activities focuses on development of all necessary data files, as well as programs and procedures which are essential to run chosen CAD tools. In our case we decided to develop ITE Process Design Kit (IDK) for CAD tools from Cadence Design Systems (CDS), as the most popular one in academia community. The only exception is synthesis, which has been implemented using Synopsys DC. The aim of last group of activities was to establish all mechanisms which are needed to run MPW service. The C3P1M2 CMOS process The basis of ITE MPW service is ITE’s proprietary CMOS process, named C3P1M2, which was developed for the purpose of ASICs manufacturing. Its key features are: single p-well, one polysilicon layer, two metalization layers. The standard process requires 12 levels of photolithography. Main structural parameters of C3P1M2 process are collected in Table 1. Process characterization The prerequisites for PDK development are parameters of technology layers specific for given process and models of silicon devices available. Process characterization stage is devoted to acquiring these data. Measurement tools The Keithley system 93 I-V, controlled by METRICS [4] software was the essential tool used for silicon devices characterization. To enable the semi-automatic measurements, it was combined with ELECT‑2002 [5] system, which controls mea[...]

Implementation of FD SOI CMOS technology in ITE


  Fully-depleted silicon-on-insulator (FD SOI) CMOS technology is widely used for fabrication of low-power, low-voltage CMOS integrated circuits (ICs) [1]. Interest in SOI CMOS technology in ITE dates to the late 90s. Different aspects of SOI technology have been considered, e.g. modelling of PD SOI MOSFETs, as well as integration of CMOS on thick SOI substrates with p-n junction based detectors of ionizing radiation [2, 3]. Recent works also comprise development of FinFET-type devices for application as chemical detectors [4]. Thus a variety of SOI CMOS technologies are under continuous development. These applications, except for the FinFET-based one, have not taken advantages of FD SOI technology: better channel operation control by gate voltage, better subthreshold I-V characteristics, lower p-n junction area and capacitance, thus lower leakage, power consumption and higher speed, as well as wider range of temperature operation. In order to fill this gap, a collaboration with UCL has been undertaken, and supported by TRIADE project [5]. The collaboration aims at transferring the FD SOI CMOS technology, originally developed at UCL [1], to ITE. Main features of this process are as follows: supply voltage 3 V, threshold voltage 0.3 V, and min poly-silicon gate width 1.5 μm. In the sections below issues related to the task mentioned above are reported. SOI substrates A recommended method for fabrication of high-quality 4-inch SOI substrates (requirement of ITE facilities) consists in laser cutting of the 200 mm UNIBOND SOI wafers manufactured originally by SOITEC. At present they represent the top quality with respect to thin silicon layer properties (crystallography, Si/SiO2 interface quality, thickness, and its uniformity), which are very relevant for manufacturing of the FD SOI CMOS devices. Method and equipment for laser cutting of 200 mm wafers have been developed in ITE. In Fig.1. the way, in which the 200 mm SOI U[...]

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