Miniaturization of electronic circuits is strongly associated with miniaturization of conductive paths and pads. It also refers to thick-film technology. Fabrication of details narrower than 150 μm by using of standard screen-printing is very difficult task. There are few more precise techniques - for example photoimageable inks method [1, 2]. It enables to create even several-micrometers wide paths. The inks prepared at Institute of Electronic Materials Technology (ITME) were tested. The compatibility between such inks and LTCC (Low Temperature Cofired Ceramics) substrates was especially an object of interest. The investigations were performed at Wrocław University of Technology, Warsaw University of Technology or Dresden Technical University. The path’s resolution, inks shrinkage as well as chosen electrical and mechanical properties (electrical resistivity, solderability, adhesion, shear resistance) were determined. Fabrication The photoimageable films were made using standard screen-printing combined with photolithography [3]. A special ink was screen- printed onto the substrate (Fig. 1a). The investigated pastes had good UV-resistance and using of UV-filters was unnecessary [4]. However, they need large amount of radiation during exposing. A proper photomask caused that only selected areas of ink were polymerized by UV light (Fig. 1b). The Hibridas Exposure Unit MA-4K were used. Remaining areas stayed unpolymerized and it was possible to remove them in the next technological step - spraying with proper developing solution (Fig. 1c). The Hibridas Developer Unit SC-4K and ethanolamine solution were used. As a result pattern from the photomask was transferred onto the substrate. The last technological step was firing of achieved layer in t[...]

  Market drivers and requirements for performance pushed semiconductor devices to scaled geometries, less power, smaller sizes and lower cost. The scaling of CMOS structures “more Moore" will not be able to meet the current and future demands of the drivers due to the functional diversification of electronics, physical limits of CMOS technology and growth of costs.System on Chip (SoC) and System in Package (SiP) both are technologies which have the potential to continue the improvement in performance, size, power, and cost of electronic systems (see Fig. 1). Both technologies feature advantages and disadvantages with respect to system integration.  SoC is a way to increase functional integration by including sub-systems on a single chip which means large scaling but increased design effort. For this, more than just digital functions have to be incorporated into an integrated circuit design, e.g. analogue-to-digital and digital-to-analogue conversion.  SiP combines multiple active electronic components of different functionality, assembled in a single unit. This enables multiple functions inserted into a system or sub-system with low design effort but higher package size. A SiP may also integrate passives, MEMS, optical components and other packages. [2] The following approaches can be regarded as state of the art of SiP technologies: - Horizontal structures (Multi Chip Module as QFP, BGA or FCpackages) - Stacked structures (PoP, 3D-integration with TSVs) - Embedded structures (embedded wafer level packages (eWLP)) Three-dimensional integration is an attractive way for bringing together various functional blocks in a vertical fashion. Hence, the reduction of package sizes leads to shorter signal and power interconnects and results into lower signal propagation delay and power consumption [3]. The advances of 3D-integration can also be used for “More than Moore" approaches, where a heterogeneous syste[...]