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Oscylator pierścieniowy CMOS jako układ detekcji odkształcenia nanoczułych mikrosond krzemowych

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Standardowymi rozwiązaniami elektronicznych układów pomiarowych wychylenia mikrobelek krzemowych są piezorezystory skonfigurowane w mostki Wheastone'a [1, 2] lub tranzystory MOS [3, 4]. Istnieje możliwość wykorzystania, jako układu detekcyjnego, bardziej złożonego układu CMOS - oscylatora pierścieniowego. Układ taki reaguje na odkształcenie belki zmianą częstotliwości drgań własnych i [...]

Implementation of FD SOI CMOS technology in ITE

  Fully-depleted silicon-on-insulator (FD SOI) CMOS technology is widely used for fabrication of low-power, low-voltage CMOS integrated circuits (ICs) [1]. Interest in SOI CMOS technology in ITE dates to the late 90s. Different aspects of SOI technology have been considered, e.g. modelling of PD SOI MOSFETs, as well as integration of CMOS on thick SOI substrates with p-n junction based detectors of ionizing radiation [2, 3]. Recent works also comprise development of FinFET-type devices for application as chemical detectors [4]. Thus a variety of SOI CMOS technologies are under continuous development. These applications, except for the FinFET-based one, have not taken advantages of FD SOI technology: better channel operation control by gate voltage, better subthreshold I-V characteristics, lower p-n junction area and capacitance, thus lower leakage, power consumption and higher speed, as well as wider range of temperature operation. In order to fill this gap, a collaboration with UCL has been undertaken, and supported by TRIADE project [5]. The collaboration aims at transferring the FD SOI CMOS technology, originally developed at UCL [1], to ITE. Main features of this process are as follows: supply voltage 3 V, threshold voltage 0.3 V, and min poly-silicon gate width 1.5 μm. In the sections below issues related to the task mentioned above are reported. SOI substrates A recommended method for fabrication of high-quality 4-inch SOI substrates (requirement of ITE facilities) consists in laser cutting of the 200 mm UNIBOND SOI wafers manufactured originally by SOITEC. At present they represent the top quality with respect to thin silicon layer properties (crystallography, Si/SiO2 interface quality, thickness, and its uniformity), which are very relevant for manufacturing of the FD SOI CMOS devices. Method and equipment for laser cutting of 200 mm wafers have been developed in ITE. In Fig.1. the way, in which the 200 mm SOI U[...]

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